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description the a1172 is an ultra-sensitive, pole-independent hall-effect switch with a latched digital output. it features operation at low supply currents and voltages, making it ideal for battery- operated electronics. the 1.65 to 3.5 v operating supply voltage and unique clocking algorithm reduce the average operating power requirements to less than 15 w with a 2.75 v supply. the a1172 has two push-pull output structures. omnipolar activation for the output function is available on each output structure. as such, either a north or south pole of sufficient strength turns the available outputs off or on. the a1172 contains two complementary outputs. therefore, for a fixed magnetic field, one output will be in a high voltage state and one output will be in a low voltage state. improved stability is made possible through dynamic offset cancellation using chopper stabilization, which reduces the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. this device 1172-ds, rev. 5 features and benefits ? micropower operation ? operation with either north or south pole? no magnetic orientation required during assembly ? 1.65 to 3.5 v battery operation ? chopper stabilization ? superior temperature stability ? extremely low switchpoint drift ? insensitive to physical stress ? sol id state reliability ? small size: wlcsp ( 1 mm 1 mm 0.5 mm) ? complementary, push-pull outputs eliminate need for pull-up resistor micropower ultra-sensitive hall-ef fect switch continued on the next page? package: 4 pin wlcsp (suffix cg) functional block diagram not to scale a1172 dynamic offset cancellation voutpn voutps vdd low-pass filter clock / logic latch latch amp gnd sample and hold engineering samples available on a limited basis. contact your local sales or applications support office for additional information.
micropower ultra-sensitive hall-effect switch a1172 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com a1 b1 a2 b2 includes, on a single silicon chip, a hall-voltage generator, a small- signal amplifier, chopper stabilization, a latch, and a mosfet output. the a1172 device offers magnetically optimized solutions, suitable for most applications. the wafer level chip scale package (wlcsp) is approximately only 1 mm by 1 mm by 0.5 mm. this package is smaller than most plastic packages and reduces the printed circuit board area consumed by micropower hall-effect switches. description (continued) pin-out diagram absolute maximum ratings characteristic symbol notes rating units supply voltage v dd 5v reverse supply voltage v rdd ?0.3 v output off voltage v outx 5v reverse output voltage v routx ?0.3 v output current i outx(sink) ?1 ma i outx(source) 1ma magnetic flux density b unlimited g operating ambient temperature t a range e ?40 to 85 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc terminal list table name number function voutps a1 push-pull output voutpn a2 inverted push-pull output gnd b1 ground vdd b2 connects power supply to chip selection guide part number package 1 pb-free packing* a1172ecglt 2 4 bumped wafer-level chip-scale package (wlcsp) pb-free chip with high-temperature solder balls (rohs compliant) 4000 pieces per reel 1 contact allegro ? for additional packing options. 2 allegro products sold in wlcsp package types are not intended for automotive applications. (bump-down view)
micropower ultra-sensitive hall-effect switch a1172 3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics characteristic symbol test conditions min. typ. 1 max. units electrical characteristics valid over full operating voltage range and t a = 25c supply voltage range 2 v dd operating, t a = 25c 1.65 ? 3.5 v output on voltage v out(sat) nmos on, i out = 1 ma, v dd = 2.75 v ? 100 300 mv v out(high) pmos on, i out = 1 ma, v dd = 2.75 v v dd ?300 v dd ?100 ? mv period t period ? 50 100 ms chopping frequency f c ? 200 ? khz supply slew rate 3 sr 20 ? ? v/ms supply current i dd(en) chip awake (enabled) ? ? 2.0 ma i dd(dis) chip asleep (disabled) ? ? 8.0 a i dd(av) v dd = 1.80 v ? 4 8 a v dd = 3.5 v ? 6 12 a magnetic characteristics 4 at t a = 25c and 1.8 v v dd 3.5 v operate point b ops ?3255g b opn ?55 ?32 ? g release point b rps 626? g b rpn ? ?26 ?6 g hysteresis b hys b hys = b opx ? b rpx ?6?g 1 typical values at v dd = 2.75 v. performance may vary for individual units, within the specified maximum and minimum limits. 2 magnetic operate and release points vary with supply voltage. 3 if sr < sr(min), then valid device output might be delayed for one period, t period , of device. 4 1 gauss (g) is exactly equal to 0.1 millitesla (mt).
micropower ultra-sensitive hall-effect switch a1172 4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics may require derating at maximum conditions* characteristic symbol test conditions value units package thermal resistance r ja on 1-layer pcb 347 oc/w on 4-layer pcb 147 oc/w *additional thermal information is available on the allegro website. 0 200 400 600 800 1000 1200 1400 1600 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (mw) power dissipation versus ambient temperature r q ja = 347 oc/w r q ja = 142 oc/w
micropower ultra-sensitive hall-effect switch a1172 5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com operating characteristics saturation voltage versus temperature 0 50 100 150 200 250 300 -60 -40 -20 0 20 40 60 80 100 t a (c) v out(sat) (mv) v dd = 1.65v v dd = 2.75v v dd = 3.5v saturation voltage versus supply voltage 0 50 100 150 200 250 300 1 1.5 2 2.5 3 3.5 4 v cc (v) v out(sat) (mv) 85c -40c 25c
micropower ultra-sensitive hall-effect switch a1172 6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com average supply current versus temperature 0 2 4 6 8 10 12 -60 -40 -20 0 20 40 60 80 100 t a (c) i dd(av) (ua) v dd = 1.65v v dd = 2.75v v dd = 3.5v average supply current versus supply voltage 0 2 4 6 8 10 12 1 1.5 2 2.5 3 3.5 4 v cc (v) i dd(av) ( a) 85c -40c 25c
micropower ultra-sensitive hall-effect switch a1172 7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com period versus temperature 0 10 20 30 40 50 60 70 80 90 100 -60 -40 -20 0 20 40 60 80 100 t a (c) t period (ms) v dd = 1.65v v dd = 2.75v v dd = 3.5v period versus supply voltage 0 10 20 30 40 50 60 70 80 90 100 1 1.5 2 2.5 3 3.5 4 v cc (v) t period (ms) 85c -40c 25c
micropower ultra-sensitive hall-effect switch a1172 8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com low average power internal timing circuitry activates the ic for 50 s and deacti- vates it for the remainder of the period (50 ms). a short awake time allows stabilization prior to the sampling and data-latching on the falling edge of the timing pulse. the output during the sleep state is latched in the last sampled state. the supply current is not affected by the output state. operation the voutps output switches low (turns on) when a magnetic field perpendicular to the hall element exceeds the operate point, b ops (or is less than b opn ). after turn-on, the output voltage is v out(sat) . the output transistor is capable of sinking cur- rent up to the short circuit current limit, i om , which is a mini- mum of 1 ma. when the magnetic field is reduced below the release point, b rps (or increased above b rpn ), the device output switches high (turns off). the pull-up transistor brings the output voltage to v out(high) . voutpn operates with the opposite output polarity. that is, the output is low (on) in the absence of a magnetic field. the output goes high (turns off) when sufficient field, of either north or south polarity, is presented to the device. the difference in the magnetic operate and release points is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. the push-pull outputs are capable of sourcing or sinking a maxi- mum of 1 ma. powering-on the device in a hysteresis region, between b opx and b rpx , allows an indeterminate output state. the correct state is attained after the first excursion beyond b opx or b rpx . b hys b hys v out(high) v out v out(sat) switch to low switch to low switch to high switch to high b+ b? v+ 0 0 figure 1. switching behavior of omnipolar switches. on the horizontal axis, the b+ direction indicates increasing south polarity magnetic field strength, and the b? direction indicates decreasing south polarity field strength (including the case of increasing north polarity). (a) voutps (b) voutpn b ops b opn b rpn b rps b hys b hys v out(high) v out v out(sat) switch to low switch to low switch to high switch to high b+ b? v+ 0 0 functional description 0 i dd(en) i dd(dis) t period sleep awake sample and output latched
micropower ultra-sensitive hall-effect switch a1172 9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vdd v s gnd voutpn a1172 voutps outputs 0.1 f c byp it is strongly recommended that an external bypass capacitor be connected (in close proximity to the hall element) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique. as is shown in figure 2, a 0.1 ? f capacitor is typical. extensive applications information on magnets and hall-effect devices is available in the following notes: ? hall-effect ic applications guide, an27701 ? hall-effect devices: gluing, potting, encapsulating, lead welding and lead forming an27703.1 ? soldering methods for allegro products (smd and through- hole), an26009 all are provided in allegro electronic data book, ams-702, and on the allegro web site, www.allegromicro.com. figure 2. typical application circuit applications
micropower ultra-sensitive hall-effect switch a1172 10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package cg, 4-bump wlcsp seating plane c 0.506 +0.049 ?0.051 0.955 0.020 0.955 0.020 0.500 0.500 0.500 0.500 0.227 0.228 ? 0.200 0.030 c 0.05 4x 2 1 2 1 a a b b a hall element (not to scale) b a c c b terminal #a1 mark area (substrate side) for reference only, not for tooling use dimensions in millimeters exact configuration at supplier discretion within limits shown d d x ? .160 a b 2 1 pcb layout reference view reference view of typical layout for solder pads all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances branding scale and appearance at supplier discretion standard branding reference view n = last two digits of device part number y = last digit of year of manufacture w = week of manufacture nn yww a1
micropower ultra-sensitive hall-effect switch a1172 11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2008-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. revision history revision revision date description of revision rev. 5 october 26, 2011 update selection guide

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